TCL (Tool Command Language) scripting plays a critical role in VLSI Physical Design (PD). Almost every major EDA tool—Cadence Innovus, Synopsys ICC2, PrimeTime, Design Compiler, and Tempus—relies heavily on TCL for automation, reporting, optimization, and design analysis.
This blog covers the Top 25 TCL Scripting Interview Questions and Answers for Physical Design, helping freshers and experienced engineers confidently face PD interviews.
TCL (Tool Command Language) is a high-level, interpreted scripting language widely used in EDA tools. In Physical Design, TCL is used to automate tasks such as floorplanning, placement, routing, timing analysis, and report generation.
TCL is lightweight, easy to learn, and tightly integrated with EDA tools. It allows engineers to control tool behavior, customize flows, and extract design data efficiently without manual intervention.
Variables store values in TCL and are dynamically typed.
Syntax:
set var_name value
Example:
set clk_period 2.5The puts command is used to display output.
Example:
puts "Physical Design Flow Started"
A list is a collection of elements separated by spaces.
Example:
set cell_list {U1 U2 U3}
Lists are commonly used to store cells, nets, or pins in PD scripts.
Use the lindex command.
Example:
lindex $cell_list 0This returns the first element of the list.
set and expr?| Command | Purpose |
|---|---|
| set | Assigns values |
| expr | Performs arithmetic operations |
Example:
set a 10
set b [expr $a + 5]
Loops execute commands repeatedly. Common loop types are for, foreach, and while.
Example (foreach):
foreach cell $cell_list {
puts $cell
}
TCL scripts define:
Example:
create_floorplan -core_utilization 0.7
A procedure (proc) is a reusable block of code.
Syntax:
proc proc_name {args} {
commands
}
proc print_violations {} {
set vio [report_timing -max_paths 10]
puts $vio
}
foreach_in_collection?It is used in Synopsys tools to iterate over design objects.
Example:
foreach_in_collection cell [get_cells] { puts [get_object_name $cell]
}
foreach and foreach_in_collection?| Feature | foreach | foreach_in_collection |
|---|---|---|
| Data type | TCL lists | Tool collections |
| Speed | Slower | Faster |
| Usage | General TCL | Synopsys tools |
Use square brackets [].
Example:
set area [report_area]
foreach net [get_nets] {
if {[get_attribute $net fanout] > 50} {
puts "High fanout net: [get_object_name $net]"
}
}
TCL scripts:
Example:
place_opt
Write to file:
set fp [open report.txt w]
puts $fp "Timing Report"
close $fp
source command?source executes another TCL script.
Example:
source setup.tcl
Using $argv and $argc.
Example:
set design_name [lindex $argv 0]
Answer:
if {[info exists var_name]} {
puts "Variable exists"
}
catch in TCL?catch handles errors gracefully.
Example:
catch {read_verilog design.v} result
TCL controls:
Example:
create_clock -period 2 -name CLK [get_ports clk]
report_timing -delay_type max -max_paths 5
TCL automates:
Example:
report_power
catchTCL scripting is an essential skill for Physical Design engineers, enabling automation, customization, and efficiency across the PD flow. Mastering TCL not only helps you crack interviews but also makes you highly productive in real projects.
If you are preparing for VLSI Physical Design roles, practicing these TCL questions and writing scripts regularly in Innovus or ICC2 will give you a strong edge.